(a) Field
Exemplary embodiments of the invention relate to a display device, and more particularly, to a display device with reduced layout area of a gate driving circuit and reduced power consumption.
(b) Description of the Related Art
Currently, display devices such as a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display have been widely used.
Such a display device typically includes a plurality of gate lines disposed in a row direction, a plurality of data lines disposed in a column direction, and a plurality of pixels arranged at points where the plurality of gate lines and the plurality of data lines cross each other. The plurality of pixels is typically driven by gate signals and data voltages transferred by the plurality of gate lines and the plurality of data lines.
In a display device, a plurality of clock signals may be used in a gate driving circuit for sequentially applying the gate signals to the plurality of gate lines. In such a display device, a plurality of capacitors may be included in the gate driving circuit. The capacitors occupy a large part of the layout area of the gate driving circuit and increase power consumption. That is, as the number of capacitors included in the gate driving circuit is increased, the layout area of the gate driving circuit and power consumption are increased.
Recently, display devices having minimized non-display area around a display area where images are displayed, e.g., a display device with slim bezels, have been manufactured, and researches for reducing the power consumption of the display device have been conducted.